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ICS8524
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
GENERAL DESCRIPTION
The ICS8524 is a low skew, 1-to-22 Differentialto-HSTL Fanout Buffer and a member of the HiPerClockSTM HiPerClockSTMFamily of High Performance Clock Solutions from ICS. The ICS8524 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The device is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the OE pin. The ICS8524's low output and part-to-part skew characteristics make it ideal for workstation, server, and other high performance clock distribution applications.
FEATURES
* 22 differential HSTL outputs each with the ability to drive 50 to ground * Selectable differential CLK, nCLK or LVPECL clock inputs * CLK, nCLK pair can accept the following differential input levels: LVPECL, LVDS, HSTL, SSTL, HCSL * PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL * Maximum output frequency: 500MHz * Translates any single-ended input signal (LVCMOS, LVTTL, GTL) to HSTL levels with resistor bias on nCLK input * Output skew: 80ps (maximum) * Part-to-part skew: 700ps (maximum) * Jitter, RMS: 0.04ps (typical) * LVPECL and HSTL mode operating voltage supply range: VDD = 3.3V 5%, VDDO = 1.6V to 2V, GND = 0V * 0C to 85C ambient operating temperature * Pin compatible with the SY89824L and NB100EP223
ICS
BLOCK DIAGRAM
CLK_SEL CLK nCLK PCLK nPCLK
PIN ASSIGNMENT
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 49 32 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 64 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDDO nQ13 Q13 nQ12 Q12 nQ11 Q11 nQ10 Q10 nQ9 Q9 nQ8 Q8 nQ7 Q7 VDDO
0
22 22
Q0:Q21 nQ0:nQ21
1 LE Q
OE
D
VDDO nQ6 Q6 nQ5 Q5 nQ4 Q4 nQ3 Q3 nQ2 Q2 nQ1 Q1 nQ0 Q0 VDDO
ICS8524
VDDO Q14 nQ14 Q15 nQ15 Q16 nQ16 Q17 nQ17 Q18 nQ18 Q19 nQ19 Q20 nQ20 VDDO
64-Lead TQFP E-Pad 10mm x 10mm x 1.0mm package body Y package Top View
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VDDO nc nc VDD CLK nCLK CLK_SEL PCLK nPCLK GND OE nc nc nQ21 Q21 VDDO
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ICS8524
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number 1, 16, 17, 32, 33, 48, 49, 64 2, 3, 12, 13 4 5 6 7 8 9 10 11 14, 15 18, 19 20, 21 22, 23 24, 25 26, 27 28, 29 30, 31 34, 35 36, 37 38, 39 40, 41 42, 43 44, 45 46, 47 50, 51 52, 53 54, 55 56, 57 58, 59 60, 61 62, 63 NOTE: Pullup and Name VDDO nc V DD CLK nCLK CLK_SEL PCLK nPCLK GND OE nQ21, Q21 nQ20, Q20 nQ19, Q19 nQ18, Q18 nQ17, Q17 nQ16, Q16 nQ15, Q15 nQ14, Q14 nQ13, Q13 nQ12, Q12 nQ11, Q11 nQ10, Q10 nQ9, Q9 nQ8, Q8 nQ7, Q7 nQ6, Q6 nQ5, Q5 nQ4, Q4 nQ3, Q3 nQ2, Q2 nQ1, Q1 nQ0, Q0 Pulldown refer Power Unused Power Input Input Input Input Input Power Input Output Output Output Output Output Type Description Output supply pins. No connect. Core supply pin. Pulldown Non-inver ting differential clock input pair. Pullup/ Inver ting differential clock input pair. Biased to 2/3 VCC. Pulldown Clock select input. When HIGH, selects PCLK, nPCLK inputs. Pullup When LOW, selects CLK, nCLK inputs. LVCMOS / LVTTL interface levels. Pulldown Non-inver ting differential LVPECL clock input pair. Pullup/ Inver ting differential LVPECL clock input pair. Biased to 2/3 VCC. Pulldown Power supply ground. Output enable. Controls enabling and disabling of outputs Pullup Q0:Q21, nQ0:nQ21. LVCMOS / LVTTL interface levels. Differential clock outputs. HSTL interface levels. Differential clock outputs. HSTL interface levels. Differential clock outputs. HSTL interface levels. Differential clock outputs. HSTL interface levels. Differential clock outputs. HSTL interface levels.
Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. Output Differential clock outputs. HSTL interface levels. to internal input resistors. See Table 2, Pin Characteristics, for typical values.
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LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 2. PIN CHARACTERISTICS
Symbol CIN RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical 4 37 75 Maximum Units pF K K
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs OE 0 0 1 1 CLK_SEL 0 1 0 1 Q0:Q21 LOW LOW CLK PCLK Outputs nQ0:nQ21 HIGH HIGH nCLK nPCLK
nCLK, nPCLK CLK,PCLK
Disabled
Enabled
OE
nQ0 :nQ21 Q0 :Q21
FIGURE 1. OE TIMING DIAGRAM
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LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, JA Storage Temperature, TSTG 4.6V -0.5V to VDD + 0.5V 50mA 100mA 22.3C/W (0 lfpm) -65C to 150C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA=0C TO 85C
Symbol VDD VDDO IDD IDDO Parameter Core Supply Voltage Output Power Supply Voltage Power Supply Current Output Supply Current No Load 1 Test Conditions Minimum 3.135 1.6 Typical 3.3 1. 8 Maximum 3.465 2. 0 220 Units V V mA mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA=0C TO 85C
Symbol VIH VIL IIH IIL Parameter Input High Voltage Input Low Voltage Input High Current Input Low Current OE, CLK_SEL OE, CLK_SEL -150 Test Conditions Minimum 2 -0.3 Typical Maximum VDD + 0.3 0.8 5 Units V V A A
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA=0C TO 85C
Symbol Parameter IIH IIL VPP Input High Current Input Low Current CLK, nCLK CLK, nCLK Test Conditions VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -150 0.15 1.3 VDD - 0.85 Minimum Typical Maximum 150 Units A A V V
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE 1, 2 GND + 0.5 NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for CLK and nCLK is VDD + 0.3V.
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TABLE 4D. LVPECL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA=0C TO 85C
Symbol I IH IIL VPP Parameter Input High Current Input Low Current PCLK, nPCLK PCLK, nPCLK Test Conditions VDD = VIN = 3.465V VDD = 3.465V, VIN = 0V -150 0.3 1 VDD Minimum Typical Maximum 150 Units A A V V
Peak-to-Peak Input Voltage
Common Mode Input Voltage; NOTE 1, 2 GND + 1.5 VCMR NOTE 1: Common mode voltage is defined as VIH. NOTE 2: For single ended applications, the maximum input voltage for PCLK and nPCLK is VDD + 0.3V.
TABLE 4E. HSTL DC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA=0C TO 85C
Symbol VOH VOL VOX Parameter Output High Voltage; NOTE 1 Output Low Voltage; NOTE 1 Output Crossover Voltage; NOTE 2 Test Conditions Minimum 1.0 0 40 0.6 Typical Maximum 1.4 0.4 60 1.1 Units V V % V
Peak-to-Peak Output Voltage Swing VSWING NOTE 1: Outputs terminated with 50 to ground. NOTE 2: Defined with respect to output voltage swing at a given condition.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V5%, VDDO = 1.8V0.2V, TA=0C TO 85C
Symbol fMAX tPD Parameter Output Frequency Propagation Delay; NOTE 1 Output Skew; NOTE 2, 4 Par t-to-Par t Skew; NOTE 3, 4 Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter section Output Rise/Fall Time Setup Time Hold Time Output Duty Cycle 133MHz 1.7 Test Conditions Minimum Typical Maximum 500 2.7 80 700 0.04 20% to 80% 300 1.0 0.5 49 51 52 700 Units MHz ns ps ps ps ps ns ns % %
tsk(o) tsk(pp) tjit
tR / tF tS tH odc
133 < 266MHz 48 NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
ADDITIVE PHASE JITTER
The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase noise plot and is most often the specified plot in many applications. Phase noise is defined as the ratio of the noise power present in a 1Hz band at a specified offset from the fundamental frequency to the power value of the fundamental. This ratio is expressed in decibels (dBm) or a ratio of the power in
0 -10 -20 -30 -40 -50
the 1Hz band to the power in the fundamental. When the required offset is specified, the phase noise is called a dBc value, which simply means dBm at a specified offset from the fundamental. By investigating jitter in the frequency domain, we get a better understanding of its effects on the desired application over the entire time record of the signal. It is mathematically possible to calculate an expected bit error rate given a phase noise plot.
Input/Output Additive Phase Jitter at 156.25MHz
= 0.04ps (typical)
SSB PHASE NOISE dBc/HZ
-60 -70 -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 -190 1k 10k 100k 1M 10M 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements have issues. The primary issue relates to the limitations of the equipment. Often the noise floor of the equipment is higher than the noise floor of the device. This is illustrated above. The de-
vice meets the noise floor of what is shown, but can actually be lower. The phase noise is dependant on the input source and measurement equipment.
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ICS8524
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION
1.8V0.2V 3.3V5% VDD VDD VDDO
Qx
SCOPE
nCLK, nPCLK
V
PP
HSTL
CLK, PCLK GND
nQx
Cross Points
V
CMR
GND 0V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
PART 1 nQx Qx PART 2 nQy Qy
DIFFERENTIAL INPUT LEVEL
nQx Qx nQy nQy
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK, nPCLK
80% Clock Outputs
80% VSW I N G
CLK, PCLK nQ0:nQ21 Q0:Q21
tPD
20% tR tF
20%
OUTPUT RISE/FALL TIME
nQ0:nQ21 Q0:Q21
Pulse Width t
PERIOD
PROPAGATION DELAY
VOX 60% 50% 40%
odc =
t PW t PERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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OUTPUT CROSSOVER VOLTAGE
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ICS8524
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = VDD/2 is generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1 1K CLK_IN + V_REF C1 0.1uF R2 1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, HSTL, SSTL, HCSL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 3A to 3E show interface examples for the HiPerClockS CLK/nCLK input driven by the most common driver types. The input interfaces suggested here are examples only. Please consult with the vendor of the driver component to confirm the driver termination requirements. For example in Figure 4A, the input termination applies for ICS HiPerClockS HSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation.
3.3V 3.3V
3.3V 1.8V
Zo = 50 Ohm
Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVHSTL ICS HiPerClockS LVHSTL Driver R1 50 R2 50
R3 50 LVPECL Zo = 50 Ohm
CLK
nCLK
HiPerClockS Input
HiPerClockS Input
R1 50
R2 50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN ICS HIPERCLOCKS HSTL DRIVER
BY
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84 HiPerClockS Input R4 125
3.3V 3.3V LVDS_Driv er R1 100 Zo = 50 Ohm Zo = 50 Ohm
CLK
nCLK
Receiv er
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
BY
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
BY
3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 125 R4 125 CLK Zo = 50 Ohm C2 nCLK HiPerClockS Input
R5 100 - 200
R6 100 - 200
R1 84
R2 84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER WITH AC COUPLE
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LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other differential signals. Both VSWING and VOH must meet the VPP and VCMR input requirements. Figures 4A to 4E show interface examples for the HiPerClockS PCLK/nPCLK input driven by the most common driver types. The input interfaces suggested here are examples only. If the driver is from another vendor, use their termination recommendation. Please consult with the vendor of the driver component to confirm the driver termination requirements.
3.3V 3.3V 3.3V R1 50 CML Zo = 50 Ohm PCLK
Zo = 60 Ohm 2.5V
2.5V 3.3V R3 120 SSTL Zo = 60 Ohm PCLK R4 120
R2 50
Zo = 50 Ohm nPCLK HiPerClockS PCLK/nPCLK
nPCLK
HiPerClockS PCLK/nPCLK
R1 120
R2 120
FIGURE 4A. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A CML DRIVER
FIGURE 4B. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY AN SSTL DRIVER
3.3V 3.3V 3.3V R3 125 Zo = 50 Ohm CLK Zo = 50 Ohm nCLK LVPECL R1 84 R2 84
Zo = 50 Ohm R5 100 C2 3.3V Zo = 50 Ohm LVDS C1
3.3V 3.3V
R4 125
R3 1K
R4 1K PCLK
nPCLK
HiPerClockS Input
HiPerClockS PCL K/n PC LK
R1 1K
R2 1K
FIGURE 4C. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVDS DRIVER
3.3V 3.3V 3.3V 3.3V LVPECL Zo = 50 Ohm C1 R3 84 R4 84 PCLK Zo = 50 Ohm C2 nPCLK HiPerClockS PCLK/nPCLK
R5 100 - 200
R6 100 - 200
R1 125
R2 125
FIGURE 4E. HIPERCLOCKS PCLK/NPCLK INPUT DRIVEN BY A 3.3V LVPECL DRIVER WITH AC COUPLE
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LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 5 shows a schematic example of the ICS8524. In this example, the input is driven by an ICS HiPerClockS HSTL driver. The decoupling capacitors should be physically located near the
power pin. For ICS8524, the unused clock outputs can be left floating.
Zo = 50 +
Zo = 50
-
VDDO=1.8V
R2 50
R1 50
U3
1.8V VDD=3.3V
Zo = 50 Ohm
Zo = 50 Ohm LVHSTL Driv er R9 50 R10 50
C9 0.1u
R12
1K
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
VDDO Q0 nQ0 Q1 nQ1 Q2 nQ2 Q3 nQ3 Q4 nQ4 Q5 nQ5 Q6 nQ6 VDDO
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
VDD=3.3V R11 1K
VDDO nc nc VDD CLK nCLK CLK_SEL PCLK nPCLK GND OE nc nc nQ21 Q21 VDDO VDDO nQ20 Q20 nQ19 Q19 nQ18 Q18 nQ17 Q17 nQ16 Q16 nQ15 Q15 nQ14 Q14 VDDO
VDDO Q7 nQ7 Q8 nQ8 Q9 nQ9 Q10 nQ10 Q11 nQ11 Q12 nQ12 Q13 nQ13 VDDO
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
ICS8524
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
Zo = 50 +
(U1-1)
VDDO=1.8V
(U1-16)
(U1-17)
(U1-32)
(U1-33)
(U1-48)
(U1-49)
(U1-64)
Zo = 50
-
C1 0.1uF
C2 0.1uF
C3 0.1uF
C4 0.1uF
C5 0.1uF
C6 0.1uF
C7 0.1uF
C8 0.1uF
R8 50
R7 50
FIGURE 5. ICS8524 HSTL BUFFER SCHEMATIC EXAMPLE
THERMAL RELEASE PATH
The expose metal pad provides heat transfer from the device to the P.C. board. The expose metal pad is ground pad connected to ground plane through thermal via. The exposed pad on the device to the exposed metal pad on the PCB is contacted through
SOLDER M ASK SIGNAL TRACE
solder as shown in Figure 6. For further information, please refer to the Application Note on Surface Mount Assembly of Amkor's Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology.
EXPOSED PAD SOLDER
SIGNAL TRACE
GROUND PLANE THERM AL VIA
Expose Metal Pad (GROUND PAD)
FIGURE 6. P.C. BOARD
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EXPOSED PAD THERMAL RELEASE PATH EXAMPLE
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ICS8524
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8524. Equations and example calculations are also provided.
1. Power Dissipation. The total power dissipation for the ICS8524 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
* *
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 220mA = 762.3mW Power (outputs)MAX = 32.8mW/Loaded Output pair If all outputs are loaded, the total power is 22 * 32.8mW = 721.6mW
Total Power_MAX (3.465V, with all outputs switching) = 762.3mW + 721.6mW = 1483.9mW
2. Junction Temperature. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125C.
The equation for Tj is as follows: Tj = JA * Pd_total + TA Tj = Junction Temperature JA = Junction-to-Ambient Thermal Resistance Pd_total = Total Device Power Dissipation (example calculation is in section 1 above) TA = Ambient Temperature In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming an air flow of 500 linear feet per minute and a multi-layer board, the appropriate value is 15.1C/W per Table 6 below. Therefore, Tj for an ambient temperature of 85C with all outputs switching is: 85C + 1.484W * 15.1C/W = 107.4C. This is well below the limit of 125C. This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow, and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE JA FOR 64-PIN TQFP, E-PAD FORCED CONVECTION
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 22.3C/W
200
17.2C/W
500
15.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. HSTL output driver circuit and termination are shown in Figure 7.
VDDO
Q1
VOUT RL 50
FIGURE 7. HSTL DRIVER CIRCUIT
AND
TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50 load.
Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Pd_H = (V
OH_MIN
/R ) * (V
L DDO_MAX
-V
OH_MIN
) )
Pd_L = (V
OL_MAX
/R ) * (V
L DDO_MAX
-V
OL_MAX
Pd_H = (1V/50) * (2V - 1V) = 20mW Pd_L = (0.4V/50) * (2V - 0.4V) = 12.8mW Total Power Dissipation per output pair = Pd_H + Pd_L = 32.8mW
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LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER RELIABILITY INFORMATION
JAVS. AIR FLOW TABLE FOR 64 LEAD TQFP, E-PAD
JA by Velocity (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards 22.3C/W
TABLE 7.
200
17.2C/W
500
15.1C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8524 is: 1474
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PACKAGE OUTLINE - Y SUFFIX
FOR
64 LEAD TQFP, E-PAD
-HD VERSION HEAT SLUG DOWN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS SYMBOL N A A1 A2 b c D D1 D2 E E1 E2 e L ccc D3 & E3
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ACD-HD MINIMUM NOMINAL 64 -0.05 0.95 0.17 0.09 -0.10 1.0 0.22 -12.00 BASIC 10.00 BASIC 7.50 Ref. 12.00 BASIC 10.00 BASIC 7.50 Ref. 0.50 BASIC 0.45 0 -2.0 0.60 ---0.75 7 0.08 10.0
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MAXIMUM
1.20 0.15 1.05 0.27 0.20
Reference Document: JEDEC Publication 95, MS-026 www.icst.com/products/hiperclocks.html
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LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number Marking Package Count Temperature ICS8524AY ICS8524AY 64 lead TQFP, E-Pad 160 per tray 0C to 85C ICS8524AYT ICS8524AY 64 lead TQFP, E-Pad on Tape and Reel 500 0C to 85C ICS8524AYLF ICS8524AYLF 64 lead TQFP, E-Pad 160 per tray 0C to 85C ICS8524AYLFT ICS8524AYLF 64 lead TQFP, E-Pad on Tape and Reel 500 0C to 85C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS com
The aforementioned trademark, HiPerClockSTM is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries. While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 8524AY
www.icst.com/products/hiperclocks.html
16
REV. B AUGUST 1, 2007
ICS8524
LOW SKEW, 1-TO-22 DIFFERENTIAL-TO-HSTL FANOUT BUFFER
REVISION HISTORY SHEET Rev B B B T9 Table T5 Page 1 5 6 15 16 Description of Change Added Phase Jitter to Features section. AC Characteristics Table - added Phase Jitter row. Added Additive Phase Jitter section. Updated Package Outline and Package Dimensions Table. Ordering Information Table - Added LF Marking and note Date 9/18/03 11/19/04 8/1/07
8524AY
www.icst.com/products/hiperclocks.html
17
REV. B AUGUST 1, 2007

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